Trace Termination

So; How do you know when to terminate a PCB trace or cable? Regardless of the clock or data frequency the design uses, the Effective Operating Frequency of a circuit, or trace is: Signal Frequency [GHz] = [0.35] / [Signal Transition Time {nSec}]. For signal Transition time, use the shorter value of Tr [Rise Time] or Tf [Fall Time]. For example: a design that uses a signal period of 50MHz with a 1.1nS rise time [or fall time] has an Effective Operating Frequency of 318MHz ~ which is far above the actual operating frequency [Period] of the signal. The FreqKnee = 0.5/Tr, the frequency at which most of the energy resides below.

PWB traces [or cables] should be terminated (using one of the schemes listed below) when the trace length exceeds the following: Length > tr / [ 2 x t pr ]
Where tr = Signal rise time, t pr = Signal propagation rate
For a general approximation this page uses: 150ps/inch for FR4 [Board Material], and 130pS/inch for Polimide [Board Material]. For example, using FR4 [150ps/inch] a trace with a 1.1nS rise time would need to be terminated if it exceeded 3.3 inches. The four main ways to terminate a signal trace are shown below. Calculations for Signal propagation rate [by board type], and reflection amplitude and frequency are shown after the termination examples.

As a side note: A Printed Wiring Board [PWB] trace really has no resistance [because it's very low], this page deals with Printed Wiring Board trace impedance. The resistance of a Printed Wiring Board trace has more to do with voltage drop over the signal line [trace] and nothing to do with signal reflections ~ which this page deals with. This page uses the terms Printed Wiring Board, or PWB, and Printed Circuit Card, or PCC, and Circuit Card Assembly, CCA Interchangeably. Also the information provided works for terminating a cable in addition to a board trace. Unused IC input pins which require a Resistor pull-up are not discussed on this page.

### Series Trace Termination

Series [Source] Termination should only be used with one load on the line, but only requires one resistor [R], placed near the source. Source Termination also works well when the driver impedance is less than the characteristic impedance of the line. It also causes no DC path. The Series Termination resistor [R] should be selected so that the combination of the resistor [R] and the output resistance [Zs] of the driver matches the trace impedance [Zo]. Source Termination may effect the rise time of the signal because of the RC time constant [R of resistor, C of the cable]. The driver is specified with a rise time based on some unit load [say 10pF], the rise time will be reduce to the R * C time constant with the series resistor. As the rise time is decreased the over all current demand from the driving pin is also reduced. Reducing the rise time has one benefit, reducing the Instantaneous current demand on the driver [reducing ground bounce and EMI] A series terminated line does not stop reflections [the load is still not terminated, un-matched], but it does reduce [damp] the amplitude of the ringing. If a source resistor is used with multiple loads, only the last device will see a clean edge, all the other loads will see a stair step edge [until the first reflection comes back]. The step voltage seen is equal to VO * [Zo / [R + Zs + Zo]]. The voltage drop rising over the capacitor [by time; t] is given by:
VC = 1 - e-(t/RC)

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### Parallel Trace Termination

Parallel Termination dissipates the most power (at low clock rates), but only requires one resistor. Parallel Termination will work with any number of loads. The termination resistor [R] is still selected to match the trace impedance [Zo] and may be taken to GND or Vcc [the Power Supply]. The large power dissipation occurs at low switching rates, while at faster clock rates the driver is switching all the time any how. VOH = the Voltage Output when High [watch the amount of current you can source], and VOL = Voltage Output when Low [watch the amount of current you can sink]. A reflection will occur when the termination resistor [R] does not match the trace impedance [Zo], some people set the termination resistor a bit higher then Zo to reduce the amplitude of the reflection [because the trace impedance is to low to match].

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### Thevenin Trace Termination

Thevenin Termination [or Split Termination] allows the selection of the correct voltage and impedance of the line, but don't use with floating outputs. This Termination scheme also provides a constant DC path, but the resistor values are normally twice as large as with Parallel Termination. The two resistors [R1 and R2] (in parallel) should be chosen to equal the line impedance [Zo], and the Thevenin voltage should be chosen to provide VT for the logic family being used. So the constant current demand calculation is Vcc / [R1 + R2], and the demand from the driving device is Vo / R1. ECL devices will pull the lower resistor to Vee, and not ground. Use the equations below to solve for the ECL values:
R1 = Zo * [Vcc - Vee / VT - Vee]
R2 = Zo * [Vcc - Vee / Vcc - VT]
Zo = [R1 * R2] / [R1 + R2] = Trace Impedance
VT = [R1 * Vee] + [R2 * Vcc] / [R1 + R2]

A capacitor may also be used to eliminate steady state DC current flow. See AC Trace Termination below.

The SCSI Bus uses R1 = 330 ohms, and R2 = 220 Ohms, with no blocking capacitor.
The VME Bus uses R1 = 470 ohms, and R2 = 330 Ohms, with no blocking capacitor.
The GPIB Bus uses R1 = 6.2k ohms, and R2 = 3k Ohms, with no blocking capacitor.

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### AC Trace Termination

AC Termination of a line results in the lowest power drain, but also requires two parts. Current only flows while the capacitor is charging. The termination resistor [R] is still selected to match the trace impedance [Zo], while the capacitor is selected by: Xc = [3 * Tr] / Zo. The capacitor value may be traded off to select a lower value [below 200pF] for low power consumption, or higher values for a cleaner waveform but a higher power consumption at higher frequencies.
Xc = 1 / [ 2 * 3.1415 * F * C] = Capacitive Reactance
F = Frequency of the signal, and C = the value of the Capacitor
Tr = Rise Time of the signal, and Zo = Trace Impedance.

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### Differential Trace Termination

Differential lines also require a termination resistor if the line length exceeds the data rate, from the equation at the top of the page. The termination is placed at the destination. To reduce the current consumption AC termination may be used [but not very common]. AC Termination of a line results in the lowest power drain, but also requires two parts. Current only flows while the capacitor is charging. The termination resistor [R] is still selected to match the trace impedance [Zo], while the capacitor is selected by: Xc = [3 * Tr] / Zo.
Xc = 1 / [ 2 * 3.1415 * F * C] = Capacitive Reactance
F = Frequency of the signal, and C = the value of the Capacitor
Tr = Rise Time of the signal, and Zo = Trace Impedance.

Half-Duplex Circuits, which transmit in both directions need to be terminated at both ends of the trace. So that the destination at each end has a termination resistor. Only two termination resistors are to be used. If there are other loads [transceiver] on the bus they should be left un-terminated.

Another example for Differential Trace Termination includes SCSI Terminations which reside on both sides of the bus. The center picture provides a Differential Trace Resistor Termination for the SCSI bus.

SCSI Termination methods
Passive Termination provided reliable operation in SCSI-1 systems, how ever for systems using SCSI-2 and above require active termination schemes. The primary problem is double clocking on the Strobe lines, which may occur because of a reflection. Of course the passive approach also has a constant resistive path from TERMPWR to ground. The Active approach provides a stable voltage to the terminating resistor. Another technique involves FPT [Forced Perfect Termination] which uses the high switching speed of Hot-Carrier Schottky diodes to approximate the perfect termination.

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### PWB Termination Example

The termination resistor should always be placed as close to the final destination as possible, of course Series termination, or source termination should be placed near the source. Placing the termination at the far end just at the input pin works well in many situations. For larger chips, such as FPGA's, which can be 1 inch square a technique called Fly-By termination is used. Fly-By termination places the termination past the device which puts the termination at the end of the trace. In this case Fly-By termination increases the trace length by an inch, the resistor is still an inch from the input pin, but at the end of the trace and not an inch before the input pin.

The bus should not be Y-ed [Left drawing] if the speed of the circuit and length of the trace act as a transmission line. The bus may be Y-ed if the trace does not appear as a transmission line based on the equation listed above. Normally the trace should be daisy-chained from device to device [center drawing]. Some high speed circuits like memory chips require the signal to reach all devices on the chain at the same time [right drawing]. If the circuit is Distributed, where Tr is less then 4 times Tpd you don't need to worry about the routing. How ever if the circuit is lumped then it needs to be viewed as a transmission line. A lumped circuit occurs when Tr is greater then 4 times Tpd. Tr = Rise Time of the signal, Tpd = propagation delay of the signal.

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### Board Material Values

The material the printed wiring board is fabricated with determines its dielectric constant. The dielectric constant in turn determines the time in which signals propagate over the board [Propagation velocity].

 Material Permittivity Propagation velocity Type Er Vp Teflon 2 212mm/nS Polyimide 3 173mm/nS FR4 Outer trace 2.8 - 4.5 141 - 179mm/nS FR4 Inner trace 4.5 141mm/nS Rogers 4003 3.38 --- PTFE 2.6 --- GETEK 3.8 - 4.2 --- Nelco 4000-8000 3.5 - 4.4 ---

Permittivity [dielectric constant] is a measure of the ability to support an electrostatic field related to capacitance. The units [Er] are Farads/meter. The numbers for Printed Wiring Boards [PWB] varies all over the place, and seems to be hard to control. How ever for any particular board material, Er will be lower for top traces [Microstrip] and higher for traces embedded [Stripline] within the board material.
Signal Velocity [Vp] = C / [Er]1/2. 'C' is a constant at 30cm/ns.

The graphic above shows how the Board Material's Permittivity and the Circuit's Rise Time effect the maximum allowable trace length. The blue vertical line assumes a rise time of 1.1nS, while the horizontal lines assume a particular board material [Orange for FR4, and Purple for Polyimide]. The graph indicates a trace length which exceeds Length > tr / [ 6 x t pr ]. The worst case trace length which must be terminated exceeds Length > tr / [ 2 x t pr ]. The difference between the two equations will relate to the Q of the circuit. The Q of the circuit is defined by the following calculation:
Q = (L/C)1/2/ Rs
FrequencyRing = 1 / (2 * 3.1415 *(LC)1/2)
Voltage Overshoot = V*e-3.1415/(4Q2-1)1/2

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### Signal Reflections

Ripple frequency is based on the trip delay from receiver to source. Ripple amplitude is based on the difference between load impedance and Trace impedance

Proper termination of a trace results in no reflections on the line [as shown in the first signal pulse]. If the trace is unterminated or terminated with a resistor value that does not match the trace impedance than a reflection will occur [shown in the next two signal pulses]. The period or frequency of the ripple is based on the trace length. The shorter the trace, the higher the ripple frequency. As the trace gets longer the trip delay increases and lowers the ripple frequency. The amplitude of the ripple [reflection] is based on the difference between the trace and load impedance. The larger the difference between the two impedances, the larger the ripple amplitude. The ripple frequency produced by an FR4 PWB [~150pS per inch of propagation delay] with a 2 inch trace will be 666MHz, or 1 / [2inch x 150ps x 5 trace times]. The 5 trace times = the first trace trip + 2 additional round trip delays.

The voltage reflection is based only on the rise time of the signal and is caused by the impedance mismatch [ripple amplitude], and the trace length [ripple period]. The frequency of the signal has nothing to do with the reflection, except that it appears worse at high signal frequencies. The reflection hasn't changed with signal frequency. So if the rise time of the signal is fixed at 1nS [for example], and we change the frequency of the signal from 2.5Mz to 10MHz. We see the period of the signal shorten, but the reflection remains unchanged in both frequency and amplitude ~ it just consumes more of the signal.

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### Reflection Coefficient Calculation

The reflection coefficient used below is based on the following equations, the numbers provided are used in the example to follow.
The Source Reflection [going from the source to the destination] = PS
PS = [ZS - ZO] / [ZS + ZO] ....... [20 - 70] / [20 + 70] = -0.55

The Load Reflection [going from the destination to the source] = Pi
Pi = [Zi - ZO] / [Zi + ZO] ....... [20k - 70] / [20k + 70] = +0.99

The maximum value for the reflection coefficient is +/-1. If the device impedance is larger then the trace impedance, the reflection coefficient is positive. If the impedance is smaller then the trace impedance, the reflection coefficient is negative.
The starting voltage from the source is based on the voltage division between ZS and ZO:
VOH [min] * [ZO / [ZS + ZO]] ....... [2.9v] / [70 / [20 + 70]] = +2.2 volts.
It's 2.9 volts [VOH] for a 3.3 volt CMOS output, +5 volt parts or TTL devices will have a different value.

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### Circuit Reflection Example

The above figure shows a typical circuit, with one driver and one receiver. The driver has a [internal] source resistance of 20 ohms, the trace impedance is 70 ohms and the input resistance on the receiver is 20k ohms. The line has not been terminated, the 20k is the internal impedance of the device.

The lattice diagram gives the voltage for both source and destination after each reflection. The waveforms are shown to the right, Green for Source, Blue for Destination. The difference in [switching] time is based on the trip delay. The source or destination will switch one trip delay from one another [1.05nS in this example]. The times provided are dependent on the trace length. The important points are 'A' and 'B'. Point 'A' is an over voltage [Overshoot] at the destination, which is given as maximum VIN in the data sheet. Point 'B' is an under voltage [Undershoot], or loss of noise margin. Noise Margin VNH is the difference between VOH min - VIH min, or 2.9v - 2.0v = 0.9v = VNH. In this case the destination sees 2.2v instead of 2.9v which is a normal minimum VOH, so VNH = 2.2v - 2.0v = 0.2 volt noise margin.
Another common source impedance is 13 ohms [instead of the 20 ohms listed], which produces an even greater magnitude in reflections. Again, the maximum value for the reflection coefficient is +/-1. The voltage at either the source or destination in the graphic above is based on the sum of the; current voltage + incoming reflection voltage + outgoing reflection voltage.
If this is a data line than the loss of noise margin is a don't care, unless the clock gates the circuit at this time. It gets harder with a 32 bit bus, with each line [reflection] shifting by 150pS [per inch] for each trace length ~ so you have to check them all. The problem compounds if the trace is a clock line ~ a double rising edge pulse on the clock line.

Reducing the Source resistor [ZS] to a more realistic value of 13 ohms, and leaving the destination unterminated produces the following change:
VOH [min] * [ZO / [ZS + ZO]] changes to 2.44 volts [instead of 2.2v].
The Source reflection coefficient is now –0.69 [instead of –0.5].
The larger initial voltage and higher reflection coefficient will produce more severe reflections [ringing].

So this low output impedance is more in line with what you might find. Most devices have a high input impedance and a low output impedance. With the new low level [1.77v] at the receiving device [blue line], the noise margin is gone. The incoming 1.77 volt signal is both an invalid voltage level and with the next rising edge ~ the second clock transition [if the signal is a clock].
In addition PWB trace impedances are hard to control, so it will vary from what may have been specified. Also, the output impedance of the driver [ZS] may be dynamic and may change with current demand or vary from device to device. Finally, the input impedance of the receiver [Zi] will normally be much greater then the 20k shown. Most devices will have FET inputs, so Zi will be infinite resulting in a reflection coefficient of 1 instead of the 0.99 used. To make matters worse there may be other reflections occurring on the traces above which are not shown. Reflections due to trace via's, moving from one PWB layer to another, or other devices on the line may reduce the 1.77v low level shown above even more.

Another more complex example would be to allow the trace impedance to change, because it passed to another layer in the PWB. Keeping the same Input and output IC impedance while changing the trace impedance results in the lattice diagram below. The interesting point here [other then the more complex voltage calculations] is that the first trace may have one length while the second trace segment has another. So reflection 'd' may not intersect with reflection 'e' ~ they occur at different times. The example for different trace segments is shown as the smaller lattice diagram to the far right [below]. The resulting reflection will no longer appear has a damped SIN wave, and will look more complex. The reflection wave-forms shown in the first two examples above are damped SIN waves {signals don't really have 0 rise times], they are just drawn as square waves because that's how it's normally shown...

The circuit shown above shows a PWB trace running on one layer of the board as a 50 ohm trace and then running on another layer as a 70 ohm trace. Keep in mind that as the trace transitioned from one layer to another it passed through a via, which is normally considered to be a low pass filter. A via is also an uncontrolled [unknown] impedance. So the graphic above should also show another [Zo] to represent the via. The equations are presented below:

Vi = Vs * [Zo1 / (Zs + Zo1)]          = 2.9 * (50 / (13 + 50) = 2.3 volts
P1 = [(Zs - Zo1) / (Zs + Zo1)]         = ((13 - 50) / (13 + 50)) = -0.587
P2 = [(Zo2 - Zo1) / (Zo2 + Zo1)]       = ((70 - 50) / (70 + 50)) = +0.167
P3 = [(Zo1 - Zo2) / (Zo1 + Zo2)]       = ((50 - 70) / (50 + 70)) = -0.167
P4 = [(Zi - Zo2) / (Zi + Zo2)]          = ((20k - 70) / (20k + 70)) = 0.993

A = a,                              A' = b + e
B = a + c + d,                  B' = b + e + g + i
C = A + c + d + f + h,      C' = b + e + g + i + k + l

T2 = 1 + P2      T3 = 1 + P3

a = Vi,      b = a * T2,      c = a * P2,      d = c * P1
e = b * P4,      f = d * P2 + e * T3,      g = e * P3 + d * T2,
h = f * P1,      i = g * P4,      j = h * P2 + i * T3,      k = i * P3 + h * T3,      l = k * P4

So solving the equations above gives these results:
A = 2.3 volts = a = Vi, the starting step voltage on the net.
A' = 5.34 volts, which represents the over-voltage Overshoot at the destination.
B = 2.46 volts, seen at the source.
B' = 3.9 volts, seen at the destination.
C = 3.36 volts, seen at the source.
C' = 1.06 volts, which represents the under-voltage Undershoot at the destination.

So now we have an over voltage which reaches above 5 volts on a 3.3 volt circuit. We also have a voltage at the destination IC which moves from 5.34 and then down to a low of 1.06 volts. The 1.06v level is well below the 1.85v Threshold Voltage for a 3.3v CMOS integrated circuit. Assuming this is a clock line into a Flip Flop, it produces a double clock [before the data had a chance to change]. We can also assume that this circuit will not function correctly, and by point C' the ringing has not even damped out yet. The reflections are still occurring after point C', they are just not shown above. The reflections will damp out as an exponential decay, and will continue based on this calculation:
t = (TraceLength * (LC)1/2) / -In[PS(2*3.14*Fknee)Pi*2*2.14*Fknee)]
As a side note, you could also solve for the standing voltage between the two trace impedances ~ if there were a third IC on the net.

A few more design rules:

1.   Multiple reflections at one node algebraically add together, so three incoming reflections shown above will algebraically add together, I leave it to the reader.

2.   Three major conditions:
Matched Load: RL = Zo:     Vr / Vi = 0, No reflection.
Open Load:      RL = ∞        Vr / Vi = +1 Full reflection, with same polarity.
Shorted Load:   RL = 0:       Vr / Vi = -1 Full reflection, with inverted polarity.

3.   An unterminated line to an IC will normally have a 1Meg ohm input resistance and a 10pF input capacitance for an impedance of (R2 + XC 2) 1/2 = 1Meg Ohm. Most Integrated Circuits will be CMOS devices with FET input circuits.

4.   A PWB trace has a very small resistance and offers no real attenuation to the reflection. The impedance [Zo] of a PCB trace;
Zo = ([R + XL] / XC)1/2

5.   A signal is attenuated as it propagates down the net by: e-TL * [(RW + jXL) * (XC) )]1/2
RW = 2 * 3.1415 * Freq. * R = Skin effect on trace resistance.
XL = 2 * 3.1415 * Freq. * L = Inductor impedance at some frequency.
XC = 2 * 3.1415 * Freq. * C = Capacitor impedance at some frequency.
TL = Trace length

6.   If a load is terminated correctly "matched" [using one of the options listed at the top of the page] no reflection will occur. If the load is unterminated a reflection will occur. If the net goes into a CLK of a flip flop the device may be double clocked, as shown above. Not having a termination is what causes ringing on Transmission lines.

7.   The Initial voltage amplitude on the line is equal to: Vs * [Zo / (Zs + Zo)], the final voltage on the line is equal to: Vs * [Zi / (Zs + Zi)]. The final voltage occurs after the transmission line effects have dissipated. In both cases, it's just a simple voltage divider.

8.   Small changes in either the source resistance [impedance] or trace impedance have a major impact on the reflections [oscillations] on the net. Changing the source resistance 7 ohms, [20 ohms to 13 ohms shown above] caused the circuit to malfunction. The circuit designer has no control over the internal source resistance of a device, and little control over the trace impedance. Assume a 20% deviation in trace impedance from what was specified, and at least a 20% change in source resistance. However, I would not bet the design on characteristics which I could not control ~ the save bet is add the termination if required.

9.   Some circuit designs require the reflection to build up the voltage on the line. Circuit designs which require the reflection are termed reflected wave switching. These designs have accounted for the issues discussed on this page.

10.   Discontinuities in the trace impedance cause reflections. A discontinuity may be caused by a trace corner, bend, a necked trace [to fit between pins] an IC pin, or trace vias. Discontinuities are not covered on this page; however, the trace mismatch is small but still produces a reflection. The reflection results are much more complex as the number of discontinuities grow.

11.   The oscillations [ringing] rise / fall time is based on the circuit [trace] or cable characteristics.

12.   As stated above, some of the resistor termination networks don't always terminate the line to the exact value of the trace. It is possible to get the values close to reduce the amount of the reflection, and still use a different resistor value. A designer may do this to use a resistor value already called out in the parts list, or because the value would be so low the driver IC may not correctly drive the load.

13.   Simulation of the circuit will account for any issue listed here. The circuit should be simulated for any trace length which exceeds Length > tr / [ 6 x t pr ]. The trace must be terminated for any trace length which exceeds Length > tr / [ 2 x t pr ]. The length will change as the logic family used changes, because the rise time [tr] changes for each logic family. The Signal propagation rate [t pr] depends on the board material, and is not well controlled. The propagation rate will differ for surface traces [Microstrip] or embedded traces [Stripline].

14.   Trace impedance is inversely proportional to trace width and directly proportional to trace height above the ground plane. Here are a few examples:
Microstrip at 50 ohms; Every 0.5mil change in trace width changes the impedance by 2 ohms. For a 1mil change in distance from the ground plane is an impedance change of 8 ohms. Doubling the trace thickness results in an impedance change of 8 ohms.
Stripline at 50 ohms; Every 0.5mil change in trace width changes the impedance by 2 ohms. For a 4mil change in distance from the ground plane is an impedance change of 5 ohms. Doubling the trace thickness results in an impedance change of 5 ohms.

15.   The page uses PWB circuit trace characteristics and equations, but the same is true for any cable; coax cable, ribbon cable, twisted ribbon pair cable, or cable pair.

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Engineering Key words for this page: Glue Logic Families, CMOS, TTL, ECL, Speed, IC, Integrated Circuits, Trace Termination, Logic Types, Transmission Line, Reflection, Reflection coefficient, Ringing, Lattice Diagram, 74xx, Device Placement, CCA, Circuit Card Assembly, PWB, Printed Wiring Board, Printed Circuit Board, PCB, Printed Circuit Card, PCC, Electronic Engineering, Trace Resistance, Net, Termination Load, Unterminated, Receiver Load, Trace Load, Overshoot, Undershoot, calculations, Equation, Cable, Differential Termination, Matched Load.

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